1. Field of the Invention
The present invention relates to forming an alignment mark mask element over an alignment mark on a semiconductor substrate. More specifically, the present invention relates to using a dual-tone photoresist to form the alignment mark mask element in conjunction with a photomask from the same photoresist material, thereby enabling semiconductor device features to be formed up to a peripheral edge of the alignment mark which is protected by the mask element.
2. State of the Art
To fabricate an integrated circuit on a semiconductor substrate such as a wafer, multiple layers of conductors and insulators are patterned and formed upon one another. In order to preserve circuit continuity, it is critical that each layer is aligned to a previous layer with great precision and accuracy. The alignment of layers is conventionally accomplished using a wafer stepper. The wafer stepper transfers a desired pattern situated on a reticle or mask onto a layer formed on the semiconductor wafer. In a typical alignment operation, the semiconductor wafer is coated with a transparent photosensitive material, such as a photoresist, and loaded into the wafer stepper. The wafer stepper uses an alignment mark on the semiconductor wafer as a reference point to adjust the position of the reticle over the semiconductor wafer to precisely align the reticle to the previous layer on the semiconductor wafer. The alignment mark is also referred to as a xe2x80x9cfiducial markxe2x80x9d or a xe2x80x9ccombi mark.xe2x80x9d
The wafer stepper uses a laser beam with a fixed wavelength to sense the position of the alignment mark on the semiconductor wafer. Light from the laser beam is reflected off the alignment mark to create a diffraction pattern. The diffraction pattern from the alignment mark is reflected to sensing devices in the wafer stepper and is used as a signal to indicate the exact position of the alignment mark. The signals are analyzed and used to determine the position of the alignment mark. The alignment mark on the semiconductor wafer is then aligned with corresponding marks on other layers, such as a photomask.
Referring to FIG. 1, an alignment mark 5 is formed by etching a semiconductor wafer 10 to create a trench or plurality of trenches or grooves in a surface of the semiconductor wafer 10. The trenches or grooves of the alignment mark are typically formed in known areas of the semiconductor wafer 10 and have a known pattern, orientation and spatial relationship. As illustrated in FIG. 1, the alignment mark 5 is usually formed along a peripheral edge of the semiconductor wafer 10 or near scribe lines that separate locations of semiconductor dice 15 on the semiconductor wafer 10. The trenches or grooves of the alignment mark 5 create a difference in step height in the semiconductor wafer 10, which is detected when the laser beam is reflected off the alignment mark 5 or a layer thereover. Integrated circuits of the semiconductor dice 15 are typically not formed on or near the alignment marks 5, thereby making these portions of the semiconductor wafer 10 wasted space or xe2x80x9creal estatexe2x80x9d on or immediately adjacent to which semiconductor dice 15 cannot be formed.
After the indicia of the alignment mark 5 have been etched into the semiconductor wafer 10, additional layers of material are deposited to form the desired integrated circuits elsewhere on the substrate, the layers also incidentally being deposited over alignment mark 5. These additional layers are, in turn, patterned and etched to form field isolation regions, polysilicon conductors, or interlayer dielectrics on the semiconductor wafer 10. Depending on the material composition of these additional layers, the alignment mark 5 can become optically invisible when additional layers are deposited over the alignment mark 5. However, since these additional layers are typically deposited conformally, the step height of the alignment mark is transferred into the subsequently deposited layers. Therefore, the transferred alignment mark remains optically visible and may still be used for alignment purposes. In addition, some of the additional layers are optically transparent and, therefore, the alignment mark remains visible through these layers.
Integrity of the alignment mark is commonly adversely affected during subsequent processing steps. For example, the alignment mark or transferred alignment mark is damaged by abrasive polishing techniques such as chemical mechanical polishing (xe2x80x9cCMPxe2x80x9d). CMP techniques are not tightly controlled at the edges of the semiconductor wafer, where the alignment marks are located, because no integrated circuits are located there. Therefore, it is common to overpolish when using CMP techniques and to remove portions of the semiconductor wafer in which the alignment mark is formed. In addition, CMP techniques may remove the alignment marks or flatten the edges of the alignment marks so that the necessary reflection off the alignment mark by the laser beam is not obtained.
Various solutions to recover or repair damaged alignment marks have been proposed. See, for example, U.S. Pat. No. 6,290,631 to Chu et al., U.S. Pat. No. 6,261,918 to So, U.S. Pat. No. 6,271,602 to Ackmann et al., U.S. Pat. No. 6,368,972 to Maury et al., and U.S. Pat. No. 6,350,658 to Miraglia et al. In addition, solutions to protect the alignment marks have been proposed. In both U.S. Pat. No. 6,342,426 to Li et al. and U.S. Pat. No. 6,326,278 to Komuro, a photoresist layer is formed on an underlying conductive layer, which extends over an alignment mark. The photoresist is patterned for etching of the conductive layer and to leave a protective metal layer portion over the alignment mark.
U.S. Pat. No. 6,417,076 to Holscher et al., assigned to the assignee of the present invention and the disclosure of which is incorporated herein by reference, discloses an approach to protecting alignment marks by depositing a globule of protective material over the alignment marks and, in some instances, at least partially over conductive patterning adjacent an alignment mark to protect same.
It would be desirable to form an alignment mark mask element over the alignment mark in the course of forming a photomask so that the alignment mark is protected from damage by subsequent processing steps. In addition, it would be desirable to reduce the wasted space on the semiconductor wafer and to increase the number of semiconductor dice that is formed per wafer by enabling formation of semiconductor device features, such as integrated circuits, in closer proximity to alignment marks.
The present invention relates to a method of forming an intermediate semiconductor device structure. The method comprises providing a fabrication substrate such as a semiconductor wafer or other bulk substrate having a layer of semiconductor material thereon and comprising at least one alignment mark. A photoresist layer is applied over the fabrication substrate. The photoresist comprises a dual-tone resist that reverses from a positive tone to a negative tone upon exposure to radiation of an appropriate wavelength and energy level. Selected portions of the photoresist layer applied to the wafer are exposed to radiation of an appropriate wavelength at a first energy to define the location and shape of semiconductor device features at a plurality of semiconductor device locations on the fabrication substrate. Only the portion of the photoresist layer above the alignment mark is then exposed to radiation of an appropriate wavelength at a second, different energy. The photoresist layer is then developed so that the portion of the photoresist exposed to the second energy remains over the alignment mark to form a protective mask element while the portions of the photoresist exposed to the first energy are removed during developing, resulting in apertures in the photomask.
A photomask for use on a fabrication substrate is disclosed. The photomask is formed from a photoresist layer, which is selectively exposed to radiation and developed to respectively define and form apertures at selected locations. The apertures are configured to facilitate etching of desired locations of an underlying material layer to form semiconductor device features or portions thereof. Some of the apertures of the photomask may be placed at locations which extend to an outer periphery of the fabrication substrate and which are not used conventionally for fabrication of semiconductor dice. At least one alignment mark mask element is positioned to substantially shield a region of the underlying material layer which is located over an alignment mark on the fabrication substrate. The portions of the material layer which are exposed through apertures in the photomask, including those located adjacent to the alignment mark, may be etched to a location substantially adjacent a peripheral edge of the alignment mark, wherein at least one of the apertures may extend substantially to a peripheral edge of the alignment mark mask element.
An intermediate semiconductor device structure is also disclosed. The intermediate semiconductor device structure comprises a fabrication substrate having at least one alignment mark, at least one material layer over the fabrication substrate, and a photomask over the at least one material layer. The photomask comprises apertures located over at least a portion of the photoresist layer. The apertures are configured to facilitate etching of selected locations of the material layer. The photomask also comprises at least one alignment mark mask element that is positioned to substantially shield an underlying alignment mark on the fabrication substrate without shielding portions of the underlying material layer closely adjacent to the alignment mark. These unshielded portions of the material layer may be etched through apertures in the photomask placed immediately adjacent to a peripheral edge of the alignment mark to form at least portions of semiconductor device features from the underlying material layer. Accordingly, at least one of the apertures may have a boundary substantially at a peripheral edge of the alignment mark mask element.
In addition, a semiconductor device structure is disclosed. The semiconductor device structure comprises a fabrication substrate having at least one alignment mark and at least one semiconductor device feature on the fabrication substrate. The at least one semiconductor device feature abuts a peripheral edge of a coplanar material layer located over the at least one alignment mark.